Engineering: Semiconductor

This technology provides a technique for fabricating metallic structures with dimensions considerably smaller than 10 nm and the use of a focused electron beam to locally manipulate nanowires with a resolution of about 3 nm. This is the first technology to use an electron beam and achieve such a high resolution of matter manipulation.

Metallic devices hold promise for miniaturization because the electronic wavelength is much smaller in metals than in semiconductors. This technology allows users to fabricate metallic structures with dimensions around 4 nm. The method is based on the application of single linear molecules. This type of metallic decoration results in a very thin metallic wire. Researchers have discovered that in order to produce continuous homogenous wires without breaks, one has to use amorphous metals and alloys which exhibit a high adhesion to the molecule. This technology also allows the use of a focused electron beam to locally modify the shape and the morphology of nanowires with a resolution of about 3 nm. A high energy focused electron beam is used for this purpose. The beam is available in a standard transmission electron microscope. Additionally, this technology can produce a nanograin small enough that its charging energy is less than room temperature thermal fluctuation energy. Therefore, these grains can act as room temperature, single-electron tunneling transistors. Also, pronounced quantum-size effects can occur at low temperatures.

This technology could potentially lead to single-electron devices smaller than those attainable through conventional semiconductor technology or even to highly integrated quantum computers.

Applications:

• Miniaturization
• Quantum computers
• Nanowire crystallization, etching and melting
• Superconducting devices
• Single-electron devices

Benefits:

Size - The ability to create metallic structures with such small dimensions can be used to improve numerous applications.

The invention is a novel method for manufacturing porous semiconductors, including silicon (Si), gallium nitride (GaN) and silicon carbide (SiC). The method involves applying a thin, discontinuous metallic (preferably platinum) layer to a semiconductor wafer, prior to using common wet chemical etchants (e.g., hydrogen fluoride, hydrogen peroxide), to produce porous silicon (PSi) or other porous semiconductors (PGaN, PSiC).

Porous semiconductors are of interest for their novel optical, electronic, and chemical properties, with PSi being of particular interest. This technology applies a thin, discontinuous layer of metal to a semiconductor wafer before using a wet chemical etching process to produce a controlled thickness of porous semiconductor. The process can be adjusted to produce specific morphologies and desired light emission spectral and/or spatial distributions.

This technology introduces a thin, metal catalyst film (a few nanometers in thickness) onto the semiconductor wafer surface, prior to immersion in an aqueous, oxidizing solution of hydrofluoric acid and hydrogen peroxide (i.e., H2O2 metal-HF etching). This process results in the simple and effective production of porous semiconductor. The simplicity and patterning capability will enable large-scale production. PSi with various morphologies, etch depths, and luminescent properties can be produced by adjusting the type(s) of metal layer deposited (gold, platinum, or gold/palladium) as well as the dopant type and level (p+, p-, or n+) of the silicon.

Current methods for generating PSi use anodic etching. In anodic etching, a silicon wafer with attached electrodes and leads is submerged in a wet chemical bath and an electrical bias is applied to drive the etching process. While PSi is not commonly used today in optical or electrical devices, anodic etching is used routinely to generate PSi used to fabricate silicon-on-insulator (SOI) wafers for the electronics industry. A drawback of anodic etching is the extra infrastructure and complexity of applying an electrical bias to a thin wafer submerged in an etchant. At a minimum, it requires electrodes, leads, a power supply, and control electronics.

This new technology is an elegantly simple alternative to anodic etching. It is an electroless technique, i.e., external electrical bias is not required, that circumvents all electrical accessories and associated methods. This novel process is also robust, controllable, and even allows flexibility for generating PSi in selected areas rather than across the entire wafer. In addition, this technology provides up to an order of magnitude enhancement in the luminescent properties of PSi compared to those of material produced using anodic etching. Furthermore, researchers may find applications for PSi that would never be possible using anodic etching.

Applications:

• Light-emitting diodes (LEDs)
• Chemical/Biological sensors
• Compliant substrates for heteroepitaxial growth (e.g., nitrides)
• Sacrificial layers for microelectromechanical devices
• Low-dielectric interconnects

Benefits:

• Enhanced Control over Product Properties: Both the morphology and light-emitting properties (spatial profile, wavelength) of the semiconductor can be tailored as a function of metal deposited, semiconductor doping level, semi-doping type, and etch time.
• Simple and Robust Process: By using metal deposition and etching, both simple, accepted processes in microelectronics, this "contactless" technology does not require the presence of electrical contacts or other stimuli/equipment to control etching.
• Directed Area Etching/Luminescence: Selective deposition or patterning of the metal catalyst allows controlled creation of etch variations in substrates below and adjacent to the metal. This method can also create selected areas with unique emission properties.
• Promising Potential Properties: This technology might lead to in situ contacts for porous semiconductors/silicon; have potential for ten-fold better luminescent emission from PSi than that obtained from anodic etching; enhance the emission of other semiconductors beyond silicon (e.g., GaN) or enable compliant substrates for heteroepitaxy; and enable creation of PSi on a variety of substrate shapes and sizes. 

Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300.degree. C. to 800.degree. C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

A method for producing light emission, including the following steps: providing a transistor structure that includes a semiconductor base region disposed between a semiconductor emitter region and a semiconductor collector region; providing a cascade region between the base region and the collector region, the cascade region having a plurality of sequences of quantum size regions, the quantum size regions of the sequences varying, in the direction toward the collector region, from a relatively higher energy state to a relatively lower energy state; providing emitter, base and collector electrodes respectively coupled with the emitter, base, and collector regions; and applying electrical signals with respect to the emitter, base, and collector electrodes to cause and control light emission from the cascade region.