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Engineering: Semiconductor

Latest Innovations
Highly Reflective Interface for Distributed Bragg Reflectors (DBRs) Distributed Bragg Reflectors (DBRs) are a fundamental component of optical devices requiring an optical gain, such as various types of semiconductor lasers.... Read More Distributed Bragg Reflectors (DBRs) are a fundamental component of optical devices requiring an optical gain, such as various types of semiconductor lasers. Conventional methods of forming DBRs require high numbers of layers of semiconductor materials to get the desired reflective resolution. This new method of forming DBRs controls the microstructure of the layers and offers improved vertical cavity surface emitting lasers (VCSELs) and resonant cavity light emitting diodes (LEDs). This technology is a method for making a highly reflective interface for distributed Bragg reflectors (DBRs), which are used in VCSELs and resonant cavity LEDs to generate optical activity. Using Group III-V materials, the interface consists of amorphous layers that contain aluminum, which when oxidized significantly increases the refractive index. As a result, the number of layers needed for the DBR can be reduced from about 30 to 4 or 5. A key element of this technology is that by using a combination of alternating polycrystalline and amorphous materials the layers can be applied to any surface, regardless of the substrate's lattice constant. Therefore, the DBR can be created on any substrate, including glass and silicon, and has a wider range of design possibilities. Additionally, changing the thickness of the layers allows reflectors of different wavelengths to be created. Highly reflective DBRs which reflect in the short wavelength of the visible spectrum and deep into the ultraviolet wavelength can be formed by this method. This technology has been tested extensively with the most common material sets, gallium arsenide (GaAs) and gallium phosphide (GaP) systems. Benefits Enables fabrication on any surface, even silicon, widening the range of useful materials and designs. Decreased processing due to reduced number of layers Increased options for substrate material, including silicon, glass, and other low-cost options. Increased design options, particularly when integrating into electronics and optical devices Improved tolerance of temperature variation due to the DBRs more stable characteristics
High Strength Low-k Insulators A polymer comprises at least two types of monomer units selected from: (1) diethynyl benzene units, (2) triethynyl benzene units, and (3) ester units. After curing... Read More A polymer comprises at least two types of monomer units selected from: (1) diethynyl benzene units, (2) triethynyl benzene units, and (3) ester units. After curing, the polymer may form a condensed polyaromatic dielectric having a dielectric constant of at most 2.0 at 1 MHz, an elastic modulus of at least 7.7 GPa, and a hardness of at least 2.0 GPa.
Sub-10 nm fabrication: molecular templating, electron-beam sculpting and crystallization of metallic nanowires This technology provides a technique for fabricating metallic structures with dimensions considerably smaller than 10 nm and the use of a focused electron beam to... Read More This technology provides a technique for fabricating metallic structures with dimensions considerably smaller than 10 nm and the use of a focused electron beam to locally manipulate nanowires with a resolution of about 3 nm. This is the first technology to use an electron beam and achieve such a high resolution of matter manipulation. Metallic devices hold promise for miniaturization because the electronic wavelength is much smaller in metals than in semiconductors. This technology allows users to fabricate metallic structures with dimensions around 4 nm. The method is based on the application of single linear molecules. This type of metallic decoration results in a very thin metallic wire. Researchers have discovered that in order to produce continuous homogenous wires without breaks, one has to use amorphous metals and alloys which exhibit a high adhesion to the molecule. This technology also allows the use of a focused electron beam to locally modify the shape and the morphology of nanowires with a resolution of about 3 nm. A high energy focused electron beam is used for this purpose. The beam is available in a standard transmission electron microscope. Additionally, this technology can produce a nanograin small enough that its charging energy is less than room temperature thermal fluctuation energy. Therefore, these grains can act as room temperature, single-electron tunneling transistors. Also, pronounced quantum-size effects can occur at low temperatures. This technology could potentially lead to single-electron devices smaller than those attainable through conventional semiconductor technology or even to highly integrated quantum computers. Applications: Miniaturization Quantum computers Nanowire crystallization, etching and melting Superconducting devices Single-electron devices Benefits: Size - The ability to create metallic structures with such small dimensions can be used to improve numerous applications.
Method For Fabricating Complex Micro and Nanoscale Electronic Structures by Sub Pixel-voting Lithography and Devices Made by Same This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices.... Read More This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The technology provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure.
Method for Fabricating Dual Damascene Profiles This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems.... Read More This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.
Curved Coupled Waveguide Array A semiconductor laser that includes an active region, claddings and electrical contacts to stimulate emissions from the active region, where a coupled waveguide... Read More A semiconductor laser that includes an active region, claddings and electrical contacts to stimulate emissions from the active region, where a coupled waveguide guides emission. The waveguide includes a broad area straight coupling region that fans out into an array of narrower Individual curved coupled waveguides at an output facet of the laser. The individual curved coupled waveguides are curved according to Lorentzian functions that define the waveguide curvature as a function of position along the device. The integral length of each individual curved coupled waveguide differs from adjacent individual curved coupled waveguides by an odd number of half-wavelengths. The coupled waveguide array shapes the optical field output of the semiconductor laser such that a large fraction of the power is emitted into a small angular distribution using interference phenomena. A laser of the invention produces high power output with a very high quality, narrow beam shape.
Direct Nanoscale Patterning of Metals Using Polymer Electrolytes Electrochemical fabrication platforms for making structures, arrays of structures and functional devices having selected nanosized and/or microsized physical... Read More Electrochemical fabrication platforms for making structures, arrays of structures and functional devices having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods, systems and system components use an electrochemical stamping tool such as solid state polymeric electrolytes for generating patterns of relief and/or recessed features exhibiting excellent reproducibility, pattern fidelity and resolution on surfaces of solid state ionic conductors and in metal. Electrochemical stamping tools are capable high throughput patterning of large substrate areas, are compatible with commercially attractive manufacturing pathways to access a range of functional systems and devices including nano- and micro-electromechanical systems, sensors, energy storage devices, metal masks for printing, interconnects, and integrated electronic circuits.
Material Assisted Laser Ablation This invention provides photoablation--based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the... Read More This invention provides photoablation--based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the fabrication of electronic, optical and opto-electronic devices. Processing techniques of the present invention enable high resolution and/or large area patterning and integration of porous and/or nano- or micro-structured materials comprising active or passive components of a range of electronic devices, including integrated circuits (IC), microelectronic and macroelectronic systems, microfluidic devices, biomedical devices, sensing devices and device arrays, and nano- and microelectromechanical systems.
Mirror Arrays for Maskless Photolithography and Image Display This invention is a class of micromirrors with high reflectivity dielectric layer coated on top of micromirror that can be tuned to allow transparency or... Read More This invention is a class of micromirrors with high reflectivity dielectric layer coated on top of micromirror that can be tuned to allow transparency or reflectivity of UV or Visible light to meet the needs of the application. Also disclosed is a top-down fabrication process for the assembly of coated micromirrors using polymer structural material. Includes additional features & methods for: phase shift mask, sharp turn off, flexible micromirror arrays, and thermal compensation.
Highly Controllable ICP Low Rate Etching of Gallium-Based III-V Semiconductor Materials A method of plasma etching Ga-based compound semiconductors includes providing a process chamber and a source electrode adjacent to the process chamber. The... Read More A method of plasma etching Ga-based compound semiconductors includes providing a process chamber and a source electrode adjacent to the process chamber. The process chamber contains a sample comprising a Ga-based compound semiconductor. The sample is in contact with a platen which is electrically connected to a first power supply, and the source electrode is electrically connected to a second power supply. The method includes flowing SiCl.sub.4 gas into the chamber, flowing Ar gas into the chamber, and flowing H.sub.2 gas into the chamber. RF power is supplied independently to the source electrode and the platen. A plasma is generated based on the gases in the process chamber, and regions of a surface of the sample adjacent to one or more masked portions of the surface are etched to create a substantially smooth etched surface including features having substantially vertical walls beneath the masked portions.

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