An innovative, cost-effective method for making and integrating fluidic microchannels. This method for ultra-rapid prototyping of microfluidic systems requiring...
An innovative, cost-effective method for making and integrating fluidic microchannels. This method for ultra-rapid prototyping of microfluidic systems requiring fewer than 5 minutes from design to prototype uses liquid phase polymerization as an alternative to etching microchannels in silcone or glass.
The method consists of introducing liquid prepolymer into a plastic or glass cartridge, exposing the prepolymer to ultraviolet light through a mask to encourage photopolymerization and define channel geometry, removing the unpolymerized prepolymer, and rinsing the resulting microchannel.
Applications
The actuators used in this technology require nothing more than the chemicals surrounding them to monitor the chemistry, mimicking chemical balances as they are maintained in the human body. This new method is ideal for biological and medical applications requiring organic materials, no electronics or batteries, bioresponsiveness, and a single, uniform platform for processing. Potential applications include detection of biological and chemical agents, disease, and contaminants, and in vitro diagnostics and therapy devices. Other promising applications exist in the area of microelectromechanical systems (MEMS).
Benefits
The invention greatly reduces the time and cost associated with the creation of microfluidics systems and requires no experience in microfabrication techniques, no cleanroom facilities, and no expensive equipment. Easy integration enables a manufacturing environment to readily incorporate "add-on" fluidics. This new technology allows ultra rapid prototyping and iterative design, affords immediate production of components, and simplifies complex systems
The invention is a novel method for manufacturing porous semiconductors, including silicon (Si), gallium nitride (GaN) and silicon carbide (SiC). The method...
The invention is a novel method for manufacturing porous semiconductors, including silicon (Si), gallium nitride (GaN) and silicon carbide (SiC). The method involves applying a thin, discontinuous metallic (preferably platinum) layer to a semiconductor wafer, prior to using common wet chemical etchants (e.g., hydrogen fluoride, hydrogen peroxide), to produce porous silicon (PSi) or other porous semiconductors (PGaN, PSiC).
Porous semiconductors are of interest for their novel optical, electronic, and chemical properties, with PSi being of particular interest. This technology applies a thin, discontinuous layer of metal to a semiconductor wafer before using a wet chemical etching process to produce a controlled thickness of porous semiconductor. The process can be adjusted to produce specific morphologies and desired light emission spectral and/or spatial distributions.
This technology introduces a thin, metal catalyst film (a few nanometers in thickness) onto the semiconductor wafer surface, prior to immersion in an aqueous, oxidizing solution of hydrofluoric acid and hydrogen peroxide (i.e., H2O2 metal-HF etching). This process results in the simple and effective production of porous semiconductor. The simplicity and patterning capability will enable large-scale production. PSi with various morphologies, etch depths, and luminescent properties can be produced by adjusting the type(s) of metal layer deposited (gold, platinum, or gold/palladium) as well as the dopant type and level (p+, p-, or n+) of the silicon.
Current methods for generating PSi use anodic etching. In anodic etching, a silicon wafer with attached electrodes and leads is submerged in a wet chemical bath and an electrical bias is applied to drive the etching process. While PSi is not commonly used today in optical or electrical devices, anodic etching is used routinely to generate PSi used to fabricate silicon-on-insulator (SOI) wafers for the electronics industry. A drawback of anodic etching is the extra infrastructure and complexity of applying an electrical bias to a thin wafer submerged in an etchant. At a minimum, it requires electrodes, leads, a power supply, and control electronics.
This new technology is an elegantly simple alternative to anodic etching. It is an electroless technique, i.e., external electrical bias is not required, that circumvents all electrical accessories and associated methods. This novel process is also robust, controllable, and even allows flexibility for generating PSi in selected areas rather than across the entire wafer. In addition, this technology provides up to an order of magnitude enhancement in the luminescent properties of PSi compared to those of material produced using anodic etching. Furthermore, researchers may find applications for PSi that would never be possible using anodic etching.
Applications:
Light-emitting diodes (LEDs)
Chemical/Biological sensors
Compliant substrates for heteroepitaxial growth (e.g., nitrides)
Sacrificial layers for microelectromechanical devices
Low-dielectric interconnects
Benefits:
Enhanced Control over Product Properties: Both the morphology and light-emitting properties (spatial profile, wavelength) of the semiconductor can be tailored as a function of metal deposited, semiconductor doping level, semi-doping type, and etch time.
Simple and Robust Process: By using metal deposition and etching, both simple, accepted processes in microelectronics, this "contactless" technology does not require the presence of electrical contacts or other stimuli/equipment to control etching.
Directed Area Etching/Luminescence: Selective deposition or patterning of the metal catalyst allows controlled creation of etch variations in substrates below and adjacent to the metal. This method can also create selected areas with unique emission properties.
Promising Potential Properties: This technology might lead to in situ contacts for porous semiconductors/silicon; have potential for ten-fold better luminescent emission from PSi than that obtained from anodic etching; enhance the emission of other semiconductors beyond silicon (e.g., GaN) or enable compliant substrates for heteroepitaxy; and enable creation of PSi on a variety of substrate shapes and sizes.
An apparatus and a method for producing atom clusters based on a gas discharge within a hollow cathode. The hollow cathode includes one or more walls. The one or...
An apparatus and a method for producing atom clusters based on a gas discharge within a hollow cathode. The hollow cathode includes one or more walls. The one or more walls define a sputtering chamber within the hollow cathode and include a material to be sputtered. A hollow anode is positioned at an end of the sputtering chamber, and atom clusters are formed when a gas discharge is generated between the hollow anode and the hollow cathode.
A method for producing light emission, including the following steps: providing a transistor structure that includes a semiconductor base region disposed between a...
A method for producing light emission, including the following steps: providing a transistor structure that includes a semiconductor base region disposed between a semiconductor emitter region and a semiconductor collector region; providing a cascade region between the base region and the collector region, the cascade region having a plurality of sequences of quantum size regions, the quantum size regions of the sequences varying, in the direction toward the collector region, from a relatively higher energy state to a relatively lower energy state; providing emitter, base and collector electrodes respectively coupled with the emitter, base, and collector regions; and applying electrical signals with respect to the emitter, base, and collector electrodes to cause and control light emission from the cascade region.
This invention fabricates copper nanowires using thermal chemical vapor deposition (CVD) at temperatures of about 200 to 400 C. The method can produce vertically...
This invention fabricates copper nanowires using thermal chemical vapor deposition (CVD) at temperatures of about 200 to 400 C. The method can produce vertically aligned copper nanowires on various metallic, oxide, and plastic substrates without the need for pores, templates, catalysts, or lithography of the substrate surface. The CVD process does not use hydrogen and is compatible with standard silicon processing technologies.
Copper wires with diameters of 70 to100 nanometers and lengths of several microns can be produced and characterized. Electron emission properties have been measured and are superior to most other materials including carbon nanotubes. The processing conditions are adjusted so as to promote the growth of wires instead of films.
Applications:
Flat panel display devices
Computing
Medical imaging
Entertainment
Home appliances
Wireless communication
Remote sensors
Benefits:
Simplicity and scalability - A straightforward CVD process that uses standard equipment is utilized. This technique does not require complex substrate preparation.
Compatibility - The process is compatible with most standard semiconductor processing protocols. The wires can be grown on a wide variety of materials including metals, silicon, and plastics.
Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor...
Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300.degree. C. to 800.degree. C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
Temperature limits the sensitivity and resolution of every surface electrical potential measurement made by an AFM today. With existing AFM probes, temperature and...
Temperature limits the sensitivity and resolution of every surface electrical potential measurement made by an AFM today. With existing AFM probes, temperature and current cannot be modulated, thus it is difficult to control temperature or to measure electrical potential at the tip. This device uses an integrated resistive heating element and temperature controls to combine temperature applications with voltage measurements to remove the uncertainty of temperature in surface electrical potential measurements.
Using an integrated resistive heating element, the device has the ability to reach 1000 C and can control the temperature of the AFM probe tip to measure the tip's electrical resistance. This device makes nanoscale surface electrical potential measurements that may be a function of temperature. As this technique modulates the temperature precisely, it removes the temperature uncertainty of surface electrical potential measurements. Using multiple probes on a single chip, the device also addresses the slow-throughput of Dip Pen Nanolithography
Applications:
Semiconductor and surface science as well as repair applications in photo-mask and flat panel displays.
Benefits:
The ability to calibrate and control AFM tip temperature within 1C at temperatures greater than 1000 C. Multiple AFM probes that can be manufactured in bulk and can be addressed individually.