This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices....
This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry.
The technology provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure.
This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems....
This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device.
The invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.
This invention provides photoablation--based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the...
This invention provides photoablation--based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the fabrication of electronic, optical and opto-electronic devices. Processing techniques of the present invention enable high resolution and/or large area patterning and integration of porous and/or nano- or micro-structured materials comprising active or passive components of a range of electronic devices, including integrated circuits (IC), microelectronic and macroelectronic systems, microfluidic devices, biomedical devices, sensing devices and device arrays, and nano- and microelectromechanical systems.
This invention is a class of micromirrors with high reflectivity dielectric layer coated on top of micromirror that can be tuned to allow transparency or...
This invention is a class of micromirrors with high reflectivity dielectric layer coated on top of micromirror that can be tuned to allow transparency or reflectivity of UV or Visible light to meet the needs of the application. Also disclosed is a top-down fabrication process for the assembly of coated micromirrors using polymer structural material. Includes additional features & methods for: phase shift mask, sharp turn off, flexible micromirror arrays, and thermal compensation.
Temperature limits the sensitivity and resolution of every surface electrical potential measurement made by an AFM today. With existing AFM probes, temperature and...
Temperature limits the sensitivity and resolution of every surface electrical potential measurement made by an AFM today. With existing AFM probes, temperature and current cannot be modulated, thus it is difficult to control temperature or to measure electrical potential at the tip. This device uses an integrated resistive heating element and temperature controls to combine temperature applications with voltage measurements to remove the uncertainty of temperature in surface electrical potential measurements.
Using an integrated resistive heating element, the device has the ability to reach 1000 C and can control the temperature of the AFM probe tip to measure the tip's electrical resistance. This device makes nanoscale surface electrical potential measurements that may be a function of temperature. As this technique modulates the temperature precisely, it removes the temperature uncertainty of surface electrical potential measurements. Using multiple probes on a single chip, the device also addresses the slow-throughput of Dip Pen Nanolithography
Applications:
Semiconductor and surface science as well as repair applications in photo-mask and flat panel displays.
Benefits:
The ability to calibrate and control AFM tip temperature within 1C at temperatures greater than 1000 C. Multiple AFM probes that can be manufactured in bulk and can be addressed individually.
A method of plasma etching Ga-based compound semiconductors includes providing a process chamber and a source electrode adjacent to the process chamber. The...
A method of plasma etching Ga-based compound semiconductors includes providing a process chamber and a source electrode adjacent to the process chamber. The process chamber contains a sample comprising a Ga-based compound semiconductor. The sample is in contact with a platen which is electrically connected to a first power supply, and the source electrode is electrically connected to a second power supply. The method includes flowing SiCl.sub.4 gas into the chamber, flowing Ar gas into the chamber, and flowing H.sub.2 gas into the chamber. RF power is supplied independently to the source electrode and the platen. A plasma is generated based on the gases in the process chamber, and regions of a surface of the sample adjacent to one or more masked portions of the surface are etched to create a substantially smooth etched surface including features having substantially vertical walls beneath the masked portions.
