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Micro/Nano Scale

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Metal-Assisted Etching For Improved Porous Semiconductors The invention is a novel method for manufacturing porous semiconductors, including silicon (Si), gallium nitride (GaN) and silicon carbide (SiC). The method... Read More The invention is a novel method for manufacturing porous semiconductors, including silicon (Si), gallium nitride (GaN) and silicon carbide (SiC). The method involves applying a thin, discontinuous metallic (preferably platinum) layer to a semiconductor wafer, prior to using common wet chemical etchants (e.g., hydrogen fluoride, hydrogen peroxide), to produce porous silicon (PSi) or other porous semiconductors (PGaN, PSiC). Details Porous semiconductors are of interest for their novel optical, electronic, and chemical properties, with PSi being of particular interest. This technology applies a thin, discontinuous layer of metal to a semiconductor wafer before using a wet chemical etching process to produce a controlled thickness of porous semiconductor. The process can be adjusted to produce specific morphologies and desired light emission spectral and/or spatial distributions. How it Works This technology introduces a thin, metal catalyst film (a few nanometers in thickness) onto the semiconductor wafer surface, prior to immersion in an aqueous, oxidizing solution of hydrofluoric acid and hydrogen peroxide (i.e., H2O2 metal-HF etching). This process results in the simple and effective production of porous semiconductor. The simplicity and patterning capability will enable large-scale production. PSi with various morphologies, etch depths, and luminescent properties can be produced by adjusting the type(s) of metal layer deposited (gold, platinum, or gold/palladium) as well as the dopant type and level (p+, p-, or n+) of the silicon. Why It Is Better Current methods for generating PSi use anodic etching. In anodic etching, a silicon wafer with attached electrodes and leads is submerged in a wet chemical bath and an electrical bias is applied to drive the etching process. While PSi is not commonly used today in optical or electrical devices, anodic etching is used routinely to generate PSi used to fabricate silicon-on-insulator (SOI) wafers for the electronics industry. A drawback of anodic etching is the extra infrastructure and complexity of applying an electrical bias to a thin wafer submerged in an etchant. At a minimum, it requires electrodes, leads, a power supply, and control electronics. This new technology is an elegantly simple alternative to anodic etching. It is an electroless technique, i.e., external electrical bias is not required, that circumvents all electrical accessories and associated methods. This novel process is also robust, controllable, and even allows flexibility for generating PSi in selected areas rather than across the entire wafer. In addition, this technology provides up to an order of magnitude enhancement in the luminescent properties of PSi compared to those of material produced using anodic etching. Furthermore, researchers may find applications for PSi that would never be possible using anodic etching. Applications PSi could be used in the following emerging applications: Light-emitting diodes (LEDs) Chemical/Biological sensors Compliant substrates for heteroepitaxial growth (e.g., nitrides) Sacrificial layers for microelectromechanical devices Low-dielectric interconnects Benefits Enhanced Control over Product Properties: Both the morphology and light-emitting properties (spatial profile, wavelength) of the semiconductor can be tailored as a function of metal deposited, semiconductor doping level, semi-doping type, and etch time. Simple and Robust Process: By using metal deposition and etching, both simple, accepted processes in microelectronics, this "contactless" technology does not require the presence of electrical contacts or other stimuli/equipment to control etching. Directed Area Etching/Luminescence: Selective deposition or patterning of the metal catalyst allows controlled creation of etch variations in substrates below and adjacent to the metal. This method can also create selected areas with unique emission properties. Promising Potential Properties: This technology might lead to in situ contacts for porous semiconductors/silicon; have potential for ten-fold better luminescent emission from PSi than that obtained from anodic etching; enhance the emission of other semiconductors beyond silicon (e.g., GaN) or enable compliant substrates for heteroepitaxy; and enable creation of PSi on a variety of substrate shapes and sizes.
Highly Reflective Interface for Distributed Bragg Reflectors (DBRs) Distributed Bragg Reflectors (DBRs) are a fundamental component of optical devices requiring an optical gain, such as various types of semiconductor lasers.... Read More Distributed Bragg Reflectors (DBRs) are a fundamental component of optical devices requiring an optical gain, such as various types of semiconductor lasers. Conventional methods of forming DBRs require high numbers of layers of semiconductor materials to get the desired reflective resolution. This new method of forming DBRs controls the microstructure of the layers and offers improved vertical cavity surface emitting lasers (VCSELs) and resonant cavity light emitting diodes (LEDs). This technology is a method for making a highly reflective interface for distributed Bragg reflectors (DBRs), which are used in VCSELs and resonant cavity LEDs to generate optical activity. Using Group III-V materials, the interface consists of amorphous layers that contain aluminum, which when oxidized significantly increases the refractive index. As a result, the number of layers needed for the DBR can be reduced from about 30 to 4 or 5. A key element of this technology is that by using a combination of alternating polycrystalline and amorphous materials the layers can be applied to any surface, regardless of the substrate's lattice constant. Therefore, the DBR can be created on any substrate, including glass and silicon, and has a wider range of design possibilities. Additionally, changing the thickness of the layers allows reflectors of different wavelengths to be created. Highly reflective DBRs which reflect in the short wavelength of the visible spectrum and deep into the ultraviolet wavelength can be formed by this method. This technology has been tested extensively with the most common material sets, gallium arsenide (GaAs) and gallium phosphide (GaP) systems. Benefits Enables fabrication on any surface, even silicon, widening the range of useful materials and designs. Decreased processing due to reduced number of layers Increased options for substrate material, including silicon, glass, and other low-cost options. Increased design options, particularly when integrating into electronics and optical devices Improved tolerance of temperature variation due to the DBRs more stable characteristics
Ultrathin Dielectric Oxide Films On Silicon The technology is a chemical method for preparing ultrathin oxide films on silicon with low leakage currents and high capacitance, optimizing the electrical... Read More The technology is a chemical method for preparing ultrathin oxide films on silicon with low leakage currents and high capacitance, optimizing the electrical properties of the dielectric barrier. Details An alternative gate dielectric material will be required for scaling of microelectronic devices to continue at its present rate. The decreasing dimensions of the transistor have required thinner and thinner gate oxide films to maintain capacitance. Unfortunately, leakage currents through silicon dioxide film become too high when using films thinner than 2 nm. Alternative gate oxide materials with a higher dielectric constant have been sought, but the problem has been finding a material which will not form an interfacial layer of silicon dioxide between the high-k dielectric and silicon substrate, and can be deposited using an economically viable process. Continuous dielectric films for silicon based electronics of thicknesses far less than is possible with SiO2have been demonstrated, with high chemical purity and exceedingly low leakage current. This is accomplished through repeated condensation-hydrolysis reactions using n-propyl orthozirconate. The resulting materials will permit the best FET gate material, and when combined with other innovations, the lowest power, highest speed transistors possible. Applications The primary application for this technology is for integrated circuits; processors and memory applications are the main applications for IC (integrated circuit) technology. Examples of such applications include: Semiconductors Microelectronics fabrication Electronic chemical industries Tool manufacturing Other applications would include sealing or passivation of silicon surfaces in electronics and capacitors on chips. Benefits Smaller, Faster, & More Efficient: High dielectric constant material allows for continuation of size reduction and increased area density Increased purity: Key to this technology is the purity of the zirconium Industry potential: High dielectric constant material with low leakage currents
Improved Ion-Implanted pn Junctions in Semiconductors The invention improves the process of ion implantation and annealing, which is used to introduce dopants into a semiconductor to make pn junctions. The... Read More The invention improves the process of ion implantation and annealing, which is used to introduce dopants into a semiconductor to make pn junctions. The improvements control the motion of bulk semiconductor defects such as interstitial atoms through control of surface chemistry. This leads to a reduction of the depth and electrical resistance of the pn junction. Details The invention concerns process improvements to ion implantation and annealing technology, which is used to introduce dopants into a semiconductor in order to make pn junctions. The improvements control the motion of bulk semiconductor defects such as interstitial atoms through control of surface chemistry. The surface chemistry changes the intrinsic ability of the surface to absorb defects that diffuse to it. The preferential loss of Si interstitials keeps electrically active dopant fixed in the lattice by inhibiting the "kick out" reaction that makes such dopant atoms mobile and inactive. The interstitial loss rate is controlled by the introduction of an additional step in the annealing process. The surface chemistry also changes the interaction of electrically charged defects with charges at the surface by greatly reducing the charge buildup at the surface and therefore reducing the surface repulsion effect, which increases the activated dopant concentration. Applications This technology can be applied to almost any product that uses higher end (< 90 nm) integrated circuits. Not relevant to technologies that use lower resolution since current pn junction technology is acceptable. Examples of such applications include: Computers Communications Electronics Benefits Pn junction with reduced depth and increased dopant activation: Leads to transistor devices with higher performance Compatible with current manufacturing technologies: Avoids the large costs associated with paradigm-changing technologies Adjusted loss rate of interstitials to the surface: Offers highly controllable mechanism for defect engineering.
Nanotip Engineering Suite Developed by the University of Illinois at Urbana-Champaign, this suite of six technologies enhances multiple facets of nanolithography and scanning probe... Read More Developed by the University of Illinois at Urbana-Champaign, this suite of six technologies enhances multiple facets of nanolithography and scanning probe microscopy. The suite features multifunctional, active probe arrays that enable nanoscale and microscale printing with multiple fluids, nanotube micromachining techniques for high-resolution probe tips, fluid dispensing systems for multiple probes, and a simple electrostatic actuation method for independently lifting individual probes in a high-density probe array. Used singularly or combined, the technologies each offer unique qualities and benefits that simplify and enhance both nanolithography and scanning probe microscopy. Applications The methods and materials that these technologies utilize can be applied to all types of scanning probe nanolithography as well as scanning probe microscopy. Applications include: Biotechnology: High-density microarrays or biochips for genomics, toxicology, proteomics, and biological and chemical sensing. Semiconductors: Microelectronic components, photomask repair, and direct-write nanolithography. Imaging: High throughout scanning probe microscopy, mapping surface characteristics, and detecting surface defects. Benefits Using essentially the same equipment but with varying probes and software, Scanning Probe Microscopy (SPM) with nanoscale probes offers great potential for both nanolithography and imaging. The Nanotip Engineering Suite enhances the functionality of SPM equipment, offering benefits in applications ranging from bioscience to semiconductors. Miniaturization of semiconductor chips could be greatly advanced with the use of scanning probe nanolithography. In genomics and proteomics, biochips containing arrays of dots such as DNA fragments allow researchers to study the vast number of interactions of various proteins on a single chip. Like semiconductor chips, the development of nanoscale scanning probes has great potential benefits for the creation and study of biochips. Current scanning probe nanolithography techniques for creating high-resolution patterning have limitations in both resolution and complexity, and they use inefficient processes. The Nanotip Engineering Suite eliminates many of those limitations and improves the overall process for nanolithography as well as scanning probe microscopy. 1. Multifunctional Probe Array (TF04157) Most current scanning probe lithography methods use a single tip or tip array that must be changed if a second "ink" needs to be applied. This probe change also requires calibration in order to maintain alignment and accuracy. Ths step is both time-consuming and inefficient and also often introduces contamination. To address these issues, this technology provides a multifunctional probe array with active probes that can perform direct chemical patterningand imaging sequentially in a singlerun with accurate registration and no need for changing probes. The technology uses actuators to enable individual control of probes for up and down movement as needed. Patterns using different chemicals and ranging from nano- to microscale can be created and then imaged without risk of cross-contamination and while eliminating the inefficiencies of switching probe tips. Benefits More versatile: An active multiprobe array enables the use of probe tips of differing sizes for generating patterns of differing sizes. Redundant probe tips can also carry different chemicals simultaneously for multi-ink lithography. Faster: This technology enables patterning and imaging sequentially in a single run, eliminating the need to change probes and recalibrate. Eliminates cross-contamination: By patterning and imaging with different probes within the same array, this technology eliminates the problem of cross-contamination. Accurate: Because the tip-to-tip distance in the array is known, accurate registration between patterns is easily achieved. Precision control: An integrated thermal actuator allows control to raise or lower individual probes. 2. Probe Fabrication Method and Microcontact Printing Technique (TF02082) Scanning probe microscopes perform measurements using a probe that has a flexible cantilever beam with a sharp tip attached at the distal end. The fabrication methods for these probes have a number of major drawbacks, including time- sensitive and inefficient processes and difficulty in producing uniform sharpness. Because the cantilevers are made of inorganic thin films, high temperatures and multi-step processes are required to produce them. This new method for probe fabrication and microcontact printing eliminates these problems, while producing either a single probe or an array of probes. It uses an efficient process, lowcost materials, and produces a uniform probe profile. This technology also includes a method for microcontact printing using the fabricated probes described above with integrated elastomeric tips and a commercial scanning probe microscope. This method eliminates the costly and timeconsuming need for a photolithography mask by attaching "inks" to the probe tip and creating patterns with connecting dots. This new technique combines the sub-micrometer accuracy and features of the SPM with the chemical versatility and performance advantages of microcontact printing. Benefits Lower cost: By utilizing a substrate and sacrificial layer, probes can be fabricated at lower cost than with current fabrication methods. Additionally, the direct microcontact printing technique lowers costs by eliminating the need for a photolithographic mask. Improved efficiency: Reusing substrate templates to fabricate additional probes saves time as well as maintains consistent size and sharpness. Improved performance: Because the microcontact printing technique combines the features of the SPM with the chemical versatility and performance advantages of microcontact printing, sub-micrometer accuracy is enabled. 3. Machining Nanotube-sized Tips from Multiwalled Nanotubes (TF04162) This technology uses an electron beam machining process to sharpen boron nitride nanotubes into fine-tipped probes for use in atomic force microscopes for molecular and nanostructure imaging and surface manipulation. The nanotube probes are of high strength, high Young's modulus of elasticity, and provide high aspect ratios. Benefits High strength: Because they are formed from multi-walled nanotubes, the resulting tips are very strong. High aspect ratio: The tip's fine point and nanometer-scale size enable high aspect ratios for viewing at the atomic level, providing a significant improvement. 4. Atomic force Microscopy (AFM) Fluid Dispensing System for Probe Arrays (TF02040) To meet the need for an arrayed fluid dispensing system for multiple probes, this technology provides fabrication methods for multiple micro-channels connected to an array of fluid wells. This technology allows side-by-side probes to receive individual inks to create high-density arrays, particularly beneficial for studying biochemical substances such as DNA or proteins. Benefits Multiple Inks: Current technologies for inking nanolithography probes do not allow the placement of unique inks on each probe tip. Individual tip inking allows for application in high-density DNA and protein arrays. 5. Electrostatic Actuators for Controlling Vertical Movement of Probes(TF03110) Problems with existing electrostatic actuators include complex fabrication methods, low deflection and force generation, large footprints requiring much wafer space and widely spaced probe tips. This design and fabrication method for electrostatic actuators uses the substrate surface as an electrode, simplifying fabrication. It also results in greater deflection and force and a much smaller footprint, enabling ultrahigh density probe arrays with improved performance. Benefits Simplified fabrication: Because this system includes only one electrode (in the probe), fabrication is greatly simplified. Smaller footprint: The electrostatic force and probe stiffness are linear functions of the probe width, making the actuation method highly scalable to very small sizes, potentially enabling ultra-high density probe arrays. Better performance: High voltage differences can be applied across the electrodes, resulting in high forces and large deflections.
High Strength Low-k Insulators A polymer comprises at least two types of monomer units selected from: (1) diethynyl benzene units, (2) triethynyl benzene units, and (3) ester units. After curing... Read More A polymer comprises at least two types of monomer units selected from: (1) diethynyl benzene units, (2) triethynyl benzene units, and (3) ester units. After curing, the polymer may form a condensed polyaromatic dielectric having a dielectric constant of at most 2.0 at 1 MHz, an elastic modulus of at least 7.7 GPa, and a hardness of at least 2.0 GPa.
Sub-10 nm fabrication: molecular templating, electron-beam sculpting and crystallization of metallic nanowires This technology provides a technique for fabricating metallic structures with dimensions considerably smaller than 10 nm and the use of a focused electron beam to... Read More This technology provides a technique for fabricating metallic structures with dimensions considerably smaller than 10 nm and the use of a focused electron beam to locally manipulate nanowires with a resolution of about 3 nm. This is the first technology to use an electron beam and achieve such a high resolution of matter manipulation. Metallic devices hold promise for miniaturization because the electronic wavelength is much smaller in metals than in semiconductors. This technology allows users to fabricate metallic structures with dimensions around 4 nm. The method is based on the application of single linear molecules. This type of metallic decoration results in a very thin metallic wire. Researchers have discovered that in order to produce continuous homogenous wires without breaks, one has to use amorphous metals and alloys which exhibit a high adhesion to the molecule. This technology also allows the use of a focused electron beam to locally modify the shape and the morphology of nanowires with a resolution of about 3 nm. A high energy focused electron beam is used for this purpose. The beam is available in a standard transmission electron microscope. Additionally, this technology can produce a nanograin small enough that its charging energy is less than room temperature thermal fluctuation energy. Therefore, these grains can act as room temperature, single-electron tunneling transistors. Also, pronounced quantum-size effects can occur at low temperatures. This technology could potentially lead to single-electron devices smaller than those attainable through conventional semiconductor technology or even to highly integrated quantum computers. Applications: Miniaturization Quantum computers Nanowire crystallization, etching and melting Superconducting devices Single-electron devices Benefits: Size - The ability to create metallic structures with such small dimensions can be used to improve numerous applications.
Parallel-Kinematics Flexure Stage (PKFS) This parallel-kinematics flexure stage (PKFS) generates a motion range larger than, or at least comparable to, current commercial designs while simultaneously... Read More This parallel-kinematics flexure stage (PKFS) generates a motion range larger than, or at least comparable to, current commercial designs while simultaneously eliminating the undesired secondary motion associated with them. As opposed to traditional positioning systems, parallel kinematics systems, because of their truss-like structures, are structurally stiffer and lighter and allow for high-bandwidth operations. In addition, errors associated with fabrication tend to cancel rather than compound each other. These novel stages are able to produce pure translation, eliminating unwanted translations through the innovative coupling of parallelogram four-bar linkage mechanisms. While further reducing the inertia associated with older designs, this design also increases rigidity and stiffness. Finally, the designs facilitate easy and efficient manufacturing. This invention shows potential uses in many diverse fields, from microscopy and medicine to near-field optical sensing, fields of use where the utmost precision, control, and reliability are critical. This technology is a development in the field of nano-scale positioning stages. The meso-scale, integrated nano-positioning, XY flexure stage can deliver pure translational motion along both the X and Y axes. It accomplishes high motion-resolution while eliminating the troublesome rotational movement often associated with similar devices. Parallel kinematics ensures that the flexure stage does not accumulate errors, but rather it cancels those errors within the kinematic chain. A flexure stage is a positioning stage in which joints are created by introducing weak or flexible areas in an otherwise rigid structure. Under actuating forces, in this case stimulation, flexing at these weak points causes the stage to move, creating the desired change in position. What makes this technology stand out from the rest is the development of a new parallelogram four-bar linkage structure. This novel design generates the desired movement (or flex), without allowing the stage to rotate, and without sacrificing stability. As an example of the capabilities of these stages, the XYZ stage is capable of approximately 50 microns of motion along each axis with sub-nanometer resolution, minimum repeatability of 5nm, and a tracking bandwidth of around 100Hz. Applications: For the user who demands superior control and stability with a fast response in nano-positioning applications. Microscopy Micro-printing Near-field optical sensing Benefits This device provides users with exceptional nano-resolution control of their working stage and offers the pure translational XY and XYZ motion necessary for precision applications. Eliminates undesirable secondary rotational-motion: Stage of positioner will not rotate unpredictably and requires no external corrective devices. Reduces inertia and increases stiffness: Four-bar linkage system increases stability of stage and reduces aberrational, inertial drift. Provides larger work zone: Parallel design offers a larger working stage than that found on other devices with similar resonation frequencies and positioning resolutions. Employs highly linear kinematics: The linear design of this parallel device offers simplicity and stability while increasing user control.
Method For Fabricating Complex Micro and Nanoscale Electronic Structures by Sub Pixel-voting Lithography and Devices Made by Same This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices.... Read More This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The technology provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure.
Metal Complexes for Depositing Metal-Containing Thin Films This technology is a family of metal complexes that can be used for depositing metal compounds. Read More This technology is a family of metal complexes that can be used for depositing metal compounds.

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