The invention is a novel method for manufacturing porous semiconductors, including silicon (Si), gallium nitride (GaN) and silicon carbide (SiC). The method involves applying a thin, discontinuous metallic (preferably platinum) layer to a semiconductor wafer, prior to using common wet chemical etchants (e.g., hydrogen fluoride, hydrogen peroxide), to produce porous silicon (PSi) or other porous semiconductors (PGaN, PSiC).
Porous semiconductors are of interest for their novel optical, electronic, and chemical properties, with PSi being of particular interest. This technology applies a thin, discontinuous layer of metal to a semiconductor wafer before using a wet chemical etching process to produce a controlled thickness of porous semiconductor. The process can be adjusted to produce specific morphologies and desired light emission spectral and/or spatial distributions.
This technology introduces a thin, metal catalyst film (a few nanometers in thickness) onto the semiconductor wafer surface, prior to immersion in an aqueous, oxidizing solution of hydrofluoric acid and hydrogen peroxide (i.e., H2O2 metal-HF etching). This process results in the simple and effective production of porous semiconductor. The simplicity and patterning capability will enable large-scale production. PSi with various morphologies, etch depths, and luminescent properties can be produced by adjusting the type(s) of metal layer deposited (gold, platinum, or gold/palladium) as well as the dopant type and level (p+, p-, or n+) of the silicon.
Current methods for generating PSi use anodic etching. In anodic etching, a silicon wafer with attached electrodes and leads is submerged in a wet chemical bath and an electrical bias is applied to drive the etching process. While PSi is not commonly used today in optical or electrical devices, anodic etching is used routinely to generate PSi used to fabricate silicon-on-insulator (SOI) wafers for the electronics industry. A drawback of anodic etching is the extra infrastructure and complexity of applying an electrical bias to a thin wafer submerged in an etchant. At a minimum, it requires electrodes, leads, a power supply, and control electronics.
This new technology is an elegantly simple alternative to anodic etching. It is an electroless technique, i.e., external electrical bias is not required, that circumvents all electrical accessories and associated methods. This novel process is also robust, controllable, and even allows flexibility for generating PSi in selected areas rather than across the entire wafer. In addition, this technology provides up to an order of magnitude enhancement in the luminescent properties of PSi compared to those of material produced using anodic etching. Furthermore, researchers may find applications for PSi that would never be possible using anodic etching.
Applications:
- Light-emitting diodes (LEDs)
- Chemical/Biological sensors
- Compliant substrates for heteroepitaxial growth (e.g., nitrides)
- Sacrificial layers for microelectromechanical devices
- Low-dielectric interconnects
Benefits:
- Enhanced Control over Product Properties: Both the morphology and light-emitting properties (spatial profile, wavelength) of the semiconductor can be tailored as a function of metal deposited, semiconductor doping level, semi-doping type, and etch time.
- Simple and Robust Process: By using metal deposition and etching, both simple, accepted processes in microelectronics, this "contactless" technology does not require the presence of electrical contacts or other stimuli/equipment to control etching.
- Directed Area Etching/Luminescence: Selective deposition or patterning of the metal catalyst allows controlled creation of etch variations in substrates below and adjacent to the metal. This method can also create selected areas with unique emission properties.
- Promising Potential Properties: This technology might lead to in situ contacts for porous semiconductors/silicon; have potential for ten-fold better luminescent emission from PSi than that obtained from anodic etching; enhance the emission of other semiconductors beyond silicon (e.g., GaN) or enable compliant substrates for heteroepitaxy; and enable creation of PSi on a variety of substrate shapes and sizes.