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Method For Fabricating Complex Micro and Nanoscale Electronic Structures by Sub Pixel-voting Lithography and Devices Made by Same This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices.... Read More This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The technology provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure.
Method for Fabricating Dual Damascene Profiles This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems.... Read More This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.
Material Assisted Laser Ablation This invention provides photoablation--based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the... Read More This invention provides photoablation--based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the fabrication of electronic, optical and opto-electronic devices. Processing techniques of the present invention enable high resolution and/or large area patterning and integration of porous and/or nano- or micro-structured materials comprising active or passive components of a range of electronic devices, including integrated circuits (IC), microelectronic and macroelectronic systems, microfluidic devices, biomedical devices, sensing devices and device arrays, and nano- and microelectromechanical systems.
Patterning Methods for Stretchable Structures Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser... Read More Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser ablation patterning methods allow for efficient manufacture of large area (e.g., up to 1 mm.sup.2 or greater or 1 m.sup.2 or greater) stretchable and/or flexible electronic devices, for example manufacturing methods permitting a reduced number of steps. The techniques further provide for improved heterogeneous integration of components within an electronic device, for example components having improved alignment and/or relative positioning within an electronic device. Also described are flexible and/or stretchable electronic devices, such as interconnects, sensors and actuators.
Mirror Arrays for Maskless Photolithography and Image Display This invention is a class of micromirrors with high reflectivity dielectric layer coated on top of micromirror that can be tuned to allow transparency or... Read More This invention is a class of micromirrors with high reflectivity dielectric layer coated on top of micromirror that can be tuned to allow transparency or reflectivity of UV or Visible light to meet the needs of the application. Also disclosed is a top-down fabrication process for the assembly of coated micromirrors using polymer structural material. Includes additional features & methods for: phase shift mask, sharp turn off, flexible micromirror arrays, and thermal compensation.
Micro-Mirror with Elastomeric Universal Joint Fabricated via Micro-Masonry Dr. Seok Kim from the University of Illinois has developed a method to fabricate a silicon-based MEMS mirror and its elastomeric universal joint. This method,... Read More Dr. Seok Kim from the University of Illinois has developed a method to fabricate a silicon-based MEMS mirror and its elastomeric universal joint. This method, termed micro-masonry, can be extended to integrate elastomer and silicon components, thus enabling strong mechanical and electrical connections between two heterogeneous materials without causing the damage of elastomer. As a result, the fabricated device could exhibit 3D motion in a compact gimballess design.
AFM Cantilever for Measuring or Actuating Temperature-Dependent Electrical Potential with Nanometer-Scale Resolution Temperature limits the sensitivity and resolution of every surface electrical potential measurement made by an AFM today. With existing AFM probes, temperature and... Read More Temperature limits the sensitivity and resolution of every surface electrical potential measurement made by an AFM today. With existing AFM probes, temperature and current cannot be modulated, thus it is difficult to control temperature or to measure electrical potential at the tip. This device uses an integrated resistive heating element and temperature controls to combine temperature applications with voltage measurements to remove the uncertainty of temperature in surface electrical potential measurements. Using an integrated resistive heating element, the device has the ability to reach 1000 C and can control the temperature of the AFM probe tip to measure the tip's electrical resistance. This device makes nanoscale surface electrical potential measurements that may be a function of temperature. As this technique modulates the temperature precisely, it removes the temperature uncertainty of surface electrical potential measurements. Using multiple probes on a single chip, the device also addresses the slow-throughput of Dip Pen Nanolithography Applications: Semiconductor and surface science as well as repair applications in photo-mask and flat panel displays. Benefits: The ability to calibrate and control AFM tip temperature within 1C at temperatures greater than 1000 C. Multiple AFM probes that can be manufactured in bulk and can be addressed individually.
Microcantilever Heater-Thermometer with Integrated Temperature Compensated Strain Sensor Thermal sensitivity in piezoresistive sensors used in silicon microcantilevers makes them susceptible to unwanted signals such as temperature drift. In addition,... Read More Thermal sensitivity in piezoresistive sensors used in silicon microcantilevers makes them susceptible to unwanted signals such as temperature drift. In addition, when used in chemical sensing, current microcantilevers have difficulty testing femtogram (10-15) scale samples due to the effect of temperature variations on the mechanical signal. This invention is a microcantilever hotplate with both a resistive heater and temperature-compensated piezoresistive strain gauges that correct for the effect of temperature variations on the mechanical strain signal. This enables the ability to test samples in femtogram quantities allowing the preservation of highly valuable materials such as DNA samples or new drug compounds. In contrast, samples tested on the milligram scale prove to be costly since the samples are often discarded after testing. Microcantilevers with integrated piezoresistive strain sensors are mainly used to replace optical (laser) deflection sensing thus reducing design complexity and cost. They may also be employed in various sensing applications such as gas flow sensing, acceleration sensing, microjet measurements and bio/chemical sensing. As bio/chemical sensors, piezoresistive microcantilevers are often prepared with a selective coating that is sensitive to a specific analyte. Analyte adsorption induces static deflection of the microcantilever by creating a surface stress, thus enabling embedded piezoresistors to measure analyte adsorption on the cantilever. Microcantilevers with both resistive heaters and piezoresistors can also offer simultaneous heating and sensing. Two different cantilever designs with the same surface area have been designed with integrated heaters along the cantilever edges and a pair of piezoresistors for temperature-compensated strain gauges. The fabricated devices show successful integration of resistive heaters and piezoresistors. These microcantilever hotplates could enable simultaneous calorimetric and thermogravimeteric measurements by operating the heater and the piezoresistor pair together. Applications Thermomechanical data storage, biomorph actuation; nanoscale thermal analysis and manufacturing; material diagnostic characterization; calorimetry; and biochemical sensing. Benefits Improves response time and enhances temperature uniformity Combines resistive heaters and piezoresistors on a microcantilever, which can be used as multi-functional scanning probes Enables materials testing at the femtogram scale A pair of piezoresistors in close proximity and aligned at 45, means excellent temperature compensation: 10 percent shift in deflection sensitivity for heating up to 200 C Has a time constant less than 1 millisecond, with maximum operation temperatures greater than 1000C
Series-Input Parallel Output Multiple DC-DC Converter with Dynamic Current Sharing for High-Current DC Power Supply The combination of a unique series-input parallel-output (SIPO) circuit configuration and a sensorless current mode (SCM) technique ensures automatic and nearly perfect... Read More The combination of a unique series-input parallel-output (SIPO) circuit configuration and a sensorless current mode (SCM) technique ensures automatic and nearly perfect load sharing of multiple dc:dc converters even during fast dynamic changes. A power supply in an embodiment of the invention includes a plurality of dc--dc switching power converters, each of which has its input isolated from its output. The power converters are arranged with their respective inputs being series connected and their respective outputs being parallel connected in an embodiment of the invention. In another embodiment of the inputs are parallel connected and the outputs series connected. Each power converter includes an input filter in each of said dc--dc switching power converters and an output filter. Each power converter includes a sensorless current mode control circuit controlling its switching duty ratio. To license the entire Solar Panels portfolio, click here.
Control Methods and Circuits for Extremely Fast Response in Switching Power Converters A method for accomplishing energy changes for a power converter to minimize an impact of a disturbance. The power converter includes energy storage and switches.... Read More A method for accomplishing energy changes for a power converter to minimize an impact of a disturbance. The power converter includes energy storage and switches. The method comprises determining a nature of the disturbance, evaluating an amount of energy to be added or removed from the internal storage, and computing operating times of the switches to minimize the impact of the disturbance on outputs of the power converter.

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