Skip to main content

Electronics

Latest Innovations
Device for the Combination of Semiconductor Processes Professor Gary Eden from the University of Illinois has developed a device that leverages the recent development of efficient, flat vacuum ultraviolet/ultraviolet lamps to... Read More Professor Gary Eden from the University of Illinois has developed a device that leverages the recent development of efficient, flat vacuum ultraviolet/ultraviolet lamps to perform two or more semiconductor fabrication processes in the same chamber. This invention is expected to significantly lower the cost of manufacturing electronic devices. This invention also introduces a new photolithography process that does not require chemical processing of a photoresist in a separate tool or by wet chemical processing. This process alone will lower the cost of photolithography and make sub-200 nm resolution photolithography accessible to a broader community of users. Fig: SEMS of patterns formed in acrylic films by irradiating the films through a photomask with a 172 nm flat lamp
High Speed Single-Mode VCSELS Dr. Milton Feng, from the University of Illinois, has developed single mode Oxide-VCSELs that are able to transmit data signals over longer distances, at higher speeds... Read More Dr. Milton Feng, from the University of Illinois, has developed single mode Oxide-VCSELs that are able to transmit data signals over longer distances, at higher speeds and with better fidelity than previously possible. Using self-aligned oxidation procedure they are able to uniformly oxidize the mode selective aperture layer and achieve higher transmission rates without sacrificing fidelity. VCSELs are important for use in 3D biosensors, consumer electronics as well as industrial cutting.
Atomic Layer Deposition of Thin Films with Arrays of Microcavity Plasmas Dr. Eden from the University of IL has developed a deposition tool that can be used for plasma-enhanced atomic layer deposition. The deposition tool consist of a... Read More Dr. Eden from the University of IL has developed a deposition tool that can be used for plasma-enhanced atomic layer deposition. The deposition tool consist of a microchannel/cavity arrays that allow for even distribution of the precursor when creating thin film layers. No external plasma sources are needed and the thin films produced have a very uniform layer.
Phase and Intensity Modulator Comprising of a RE-Doped Fiber Dr. Dragic from the University of IL has developed a phase and intensity modulator using rare earth doped ytterbium fiber. The modulators are unconventional because they... Read More Dr. Dragic from the University of IL has developed a phase and intensity modulator using rare earth doped ytterbium fiber. The modulators are unconventional because they do not cause phase change through the passage of light. The fiber absorbs the light and heats up causing phase change to occur.
Carbon Nanotube Portfolio for Manufacturing Applications This portfolio includes carbon nanotube growth and processing methods relevant to nanotube manufacturing.... Read More This portfolio includes carbon nanotube growth and processing methods relevant to nanotube manufacturing. Patterned Catalyst Techniques for Aligned Single-walled Carbon Nanotube Growth Single-walled carbon nanotubes (SWNTs) feature exceptional electric properties (conductivity and semi-conductivity) that make them attractive for nano-electronics, optics, material applications and more. This SWNT growth technology yields a dense structure without degraded alignment by eliminating undesired interactions between the SWNT and catalysts on the growth surface. More specifically, a patterned catalyst is used to provide a template to direct SWNT growth, resulting in perfectly aligned high coverage SWNTS. Benefits Higher density Large scale Higher quality Applications Patterned catalyst techniques are applicable for standard electronic devices that use thin film semiconductors, such as field effect transistors (FETs), sensors, thin-film transistors (TFTs). These devices can benefit from ability to deposit SWNT onto plastics and other unusual device substrates: steerable antenna arrays, flexible displays, etc. Medium Scale Carbon Nanotube Thin Film Integrated Circuits on Flexible Plastic Substrates This technology improves the performance and consistency of integrated circuits featuring semi-conductive carbon nanotube (CNT) transistors. Specifically, metallic conductive pathways in random nanotube networks are reduced using a medium scale carbon nanotube thin film. This process reduces these pathways by cutting fine lines into the carbon nanotube network while preserving its semiconducting properties. Benefits Reduces purely metallic conductive pathways in a carbon nanotube network used to construct electronic circuits. Vastly improves carbon nanotube device consistency in production (yield). Applications Primary application is integrated circuits for flexible substrate materials. Using Nanoscale Thermocapillary Flows to Create Arrays of Purely Semiconducting Single-Walled Carbon Nanotubes This carbon nanotube (CNT) purification technology facilitates scalable, damage-free separation of arrayed metallic and semi-conductive CNTs. Resulting CNT arrays may be large and feature high Ion/Ioff ratios, allowing for less power loss while powered off, faster switching times, and overall lower operating voltage. The invention improves CNT array quality by creating a temperature gradient to release metallic CNTs from the array matrix. Benefits Less lost power while off Faster switching time Lower operating voltage
Suite of Bioresorbable and Transient Electronics Read More Transient electronic devices belong to a set of technologies, whereby traditional analog electronic circuits and components have been made in new ways. These new electronics exist on a much smaller scale and made of bioinert or biocompatible materials. They are flexible and transient. Transient and bioresorbable technologies are a class of device that have the ability to physically disappear at a programmed rate. Inventions within this suite includedevices and processes with applications rangingfrom medicine to construction, and from defense/securityto indoor/outdoor sensors. These technologies are appropriate for applications where device placement can be costly, invasive, or inconvenient to retrieve. Features Tunable to dissolve at programmed time Bio-compatible Soft, curvilinear surface Transient battery Materials: silicon, magnesium, magnesium oxide Benefits Electronics can now be implanted on surfaces with non-planar contact patches and non-invasive integration on soft, curvilinear surfaces of biological tissues and organs. Application Areas Remaking electronics with these capabilities permits for a plethora of new applications, in medicine, environmental research, biological enhancement, digital financial transactions and traceless surveillance.
Optical Inspection of Nanoscale Structures using a Novel Machine Learning Based Synthetic Image Generation Algorithm Semiconductor defect detection using Machine Learning Dr. Goddard and Dr. Schwing have developed a machine learning technique which requires only... Read More Semiconductor defect detection using Machine Learning Dr. Goddard and Dr. Schwing have developed a machine learning technique which requires only few training images to detect and classify nano-scale anomalies in semiconductors and in noisy optical images. It is able to automate defect inspection in a 9nm semiconductor wafer with high accuracy and at a high speed in fabrication laboratories using visible light microscopy. This method is faster than atomic force microscopy and scanning electron microscopy, and is more sensitive than current optical microscopy. It can also be used for other applications such as dimension measurements and disease sample measurements. Sanyogita Purandare, Jinlong Zhu, Renjie Zhou, Gabriel Popescu, Alexander Schwing, and Lynford L. Goddard, "Optical inspection of nanoscale structures using a novel machine learning based synthetic image generation algorithm," Opt. Express 27, 17743-17762 (2019) Optical inspection of nanoscale structures using a novel machine learning based synthetic image generation algorithm. Sanyogita Purandare, Jinlong Zhu, Renjie Zhou, Gabriel Popescu, Alexander Schwing, Lynford L. GoddardOpt Express. 2019 Jun 24; 27(13): 17743–17762. doi: 10.1364/OE.27.017743
NetDIMM The emergence of datacenters as single computer entities has made latency a critical consideration in designing datacenter networks. PCIe interconnect is known to be a... Read More The emergence of datacenters as single computer entities has made latency a critical consideration in designing datacenter networks. PCIe interconnect is known to be a latency bottleneck in communication networks as its overhead can contribute to up to 90% of the overall communication latency. PCIe is a standard motherboard interface, sending a packet over a conventional NIC requiring several PCIe and memory channel transactions. This data movement in the network software stacks consumes thousands of processor cycles, which ultimately prevent ultra-low latency networking. Researchers eliminate NIC-PCIe transactions and instead use the local memory channels between the memory and NIC, resulting in reduced latency and improved data center computer performance (figure 1). This finding is the basis for NetDIMM, which is a method for integrating a network interface chip with the memory module of a computer. Figure 1: State of the art network interface architectures vs. NetDIMM On average, NetDIMM improves per packet latency by 49.9% compared with a baseline network deploying PCIe NICs (figure 2). The NetDIMM architecture is located in the memory module and does not require any change to the processor architecture or memory subsystem. Figure 2: One-way network latency breakdown for packets of various sizes when using a PCIe NIC (left), an integrated NIC (middle), and NetDIMM (left). X-axis is not drawn to scale. Most recently, NetDIMM was presented at the 52nd IEEE/ACM International Symposium on Microarchitecture in Columbus, Ohio. The conference publication can be accessed here.
Plasma Photonic Crystals Device with Plasmonic Resonances in the Microwave, Millimeter Wave, and Terahertz Spectral Regions Dr. Eden at the University of Illinois has developed a 3D microplasma photonic crystal which provides the ability to introduce or completely suppress attenuation... Read More Dr. Eden at the University of Illinois has developed a 3D microplasma photonic crystal which provides the ability to introduce or completely suppress attenuation resonances at will, in the microwave, millimeter wave, and terahertz spectral regions, while minimizing insertion loss. This complex 3D photonic crystal is comprised of a 3D-printed polymer scaffold, and free-standing arrays of polyimide capillaries. Since the capillaries are suspended in free space on the scaffold, electromagnetic structures can be placed on or around the microtubes. One example of this involves depositing metal films onto each capillary with precise periodicity. In this way, each pair of neighboring metal film rings in the 3D array are effectively coupled and constitute a capacitor, creating extremely versatile, and tunable crystal performance. Applications Microwave, millimiter-wave, terahertz communications, DoD/military (optical cloaking, electronic warfare)
Application Level Hardware Tracing for Scaling Post-Silicon Debug Dr. Vasudevan from the University of IL has developed an advanced algorithm for optimizing design-for-debug hardware. This algorithm takes advantage of high level... Read More Dr. Vasudevan from the University of IL has developed an advanced algorithm for optimizing design-for-debug hardware. This algorithm takes advantage of high level abstraction to enable accurate bug localization, eliminating almost 90% of possible root causes in tests using an industrial SoC. This technology, which is broadly scalable versus existing methods, addresses a great need in the field of Electronic Design Automation by decreasing the cost and shortening the timescale of chip debugging, accelerating time-to-market and streamlining the post-silicon validation phase. Application: Incorporation into chip design and verification software Publication: Pal, D.; Sharma, A.; Ray, S.; de Paula, F. M.; and Vasudevan, S. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pages 92:1–92:6, 2018.

Pages