Application Level Hardware Tracing for Scaling Post-Silicon Debug

Dr. Vasudevan from the University of IL has developed an advanced algorithm for optimizing design-for-debug hardware. This algorithm takes advantage of high level abstraction to enable accurate bug localization, eliminating almost 90% of possible root causes in tests using an industrial SoC. This technology, which is broadly scalable versus existing methods, addresses a great need in the field of Electronic Design Automation by decreasing the cost and shortening the timescale of chip debugging, accelerating time-to-market and streamlining the post-silicon validation phase.
Application: Incorporation into chip design and verification software
Publication: Pal, D.; Sharma, A.; Ray, S.; de Paula, F. M.; and Vasudevan, S. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pages 92:1–92:6, 2018.