Researchers at the University of Illinois Urbana-Champaign have developed a processor architecture that allows for greater efficiency in computing power and energy consumption. The architecture exploits parallelism through thread pipelining and an out-of-order loop system. This process is possible by utilizing more processing elements in the system. This method does create extra cost and is essentially a cost for efficiency trade-off. The system can be used in a variety of embedded systems such as CPUs and GPUs. The decrease in energy consumption can also be applied to servers and other large processing units that consumer a lot of energy and in the process and lot of heat.