This technology is a method for making modifications to semiconductor wafers on an atomic scale, creating "nanowires" or "nanoclusters" on a commercially viable scale. These types of modifications will become more important as the line-widths of processors decrease beyond the physical limits of current production techniques. In this case, transistors and other components will have to be made at the atomic level to improve performance and speed. Estimates based on Moore's Law suggest that production techniques using atomic-level techniques will be required at line-widths of less than .05 m (currently .13 m for Pentium 4 processors), which will be required in about 10-12 years.
The invention relates to a method for forming atomic-scale structures on a surface of a substrate on a large-scale. The method includes creating a predetermined amount of surface vacancies on the surface of the substrate by removing an amount of atoms on the surface of the material corresponding to the predetermined amount of surface vacancies. Once the surface vacancies have been created, atoms of a desired structure material are deposited on the surface of the substrate to enable the surface vacancies and the atoms of the structure material to interact. This interaction causes the atoms of the structure material to form the atomic-scale structures. The method overcomes the slow production levels and narrow modification area of current techniques, which require scanning tunneling microscopes (STM) and can take months to produce a single modified 8 inch wafer. It allows parallel fabrication of the atomic level structures, which allows more rapid, large-area simultaneous production, and therefore makes production of these structures commercially viable. The structures that could be fabricated using this technology include quantum-dot devices, nano-scale interconnects, ultra-high density information devices, and nanowires.
- Quantum-dot devices
- Nano-scale interconnects
- Ultra high density information devices
- Allows parallel processing of nano-scale structures
- Compatibility with current CMOS processing technologies