Researchers at UIC have developed a low-power physical synthesis
(PS) tool DNF-PS for chip design. This
tool simultaneously applies a set of
very effective power/timing optimizing transforms (in particular, multiple Vdd, multiple Vth, cell sizing,
buffer insertion, cell replication and global re-placement), and does so
simultaneously
across the entire circuit while satisfying multiple constraints (e.g., on timing, voltage islands, area,
congestion).