Processes

Manufacturers can not achieve superconformal (bottom-up) filling of high aspect ratio features by a modified chemical vapor deposition method. The CVD precursor flux is augmented by a small flux of a growth suppressor, which slows deposition near the upper surface of the substrate while permitting growth at normal rates deep in a trench or via.

Details

As circuit densities increase, the width of their gap structures decrease, making uniform deposition of semiconductor materials more difficult and more expensive. In order to keep-up with the demand for increasing miniaturization, transistor manufacturers have developed several novel alternatives to physical layer deposition. Among the most successful of these alternatives is Atomic Layer Deposition (ALD), a technique that essentially builds thin-film depositions one atom-layer at a time. Atomic layer deposition, however, is slow and must be repeatedly exposed to alternating reactive gasses. Electrochemical Deposition (ECD) has also been used as a solution in increasing circuit densities, but ECD is limited to certain materials and requires an additional "wet processing" step. Superconformal CVD avoids these obstacles through super heating elemental hydrogen or nitrogen, changing the gas into its atomic, or plasmatic, state. During the chemical deposition process, a plasma beam that is directed at the substrate suppresses the chemical reaction along the surface of the etched wafer, preventing undesirable material accumulation around the cusp of the wafer's trenches.

Applications

For use in the development of micro- and nano-scale semiconductor devices, Superconformal CVD gives producers of microchips, MEMS, and various other microelectronic devices greater control over their manufacturing process. All current methods of CVD: Superconformal CVD has been demonstrated to be successful for the deposition of several different types of materials. The technique should be widely applicable for the superconformal deposition of essentially any material, although additional development work may be required to identify the best combination of suppressor gas and growth gas. 

Benefits

The semiconductor device industry strives to develop manufacturing techniques to meet increasingly stringent design rules. By offering a gas-phase method for achieving superconformal, bottom-up filling of features with high aspect-ratios, this technology solves a long-standing manufacturing obstacle.

• Eliminates Pinch-off: Pinch-off occurs when unwanted film deposition near the opening of a trench or via accumulates to the point that the gap closes. Pinch-off creates voids within a trench or via, resulting in reduced device performance. These problems have proven difficult to overcome; alternative manufacturing methods - atomic layer deposition (ALD) and electrochemical deposition (ECD) - require several extra steps.
• Fast and inexpensive: Our Superconformal Chemical Vapor Deposition method is fast and inexpensive and does not require extra chemical washing or polishing steps. The process is compatible with existing microelectronic manufacturing methods.
• Clean deposition: Atomic hydrogen often serves as an effective suppressor gas, and a significant advantage of its use is that impurities are not introduced that could compromise device performance. The metastable nature of the atomic hydrogen ensures that it rapidly recombines on and desorbs from the surface as molecular hydrogen gas.
• High Aspect Ratio Processes: With our improved method, pinch-off is reduced or eliminated, often achieving complete filling even for aspect ratios as high as 50:1.

The invention improves the process of ion implantation and annealing, which is used to introduce dopants into a semiconductor to make pn junctions. The improvements control the motion of bulk semiconductor defects such as interstitial atoms through control of surface chemistry. This leads to a reduction of the depth and electrical resistance of the pn junction.

Details

The invention concerns process improvements to ion implantation and annealing technology, which is used to introduce dopants into a semiconductor in order to make pn junctions. The improvements control the motion of bulk semiconductor defects such as interstitial atoms through control of surface chemistry. The surface chemistry changes the intrinsic ability of the surface to absorb defects that diffuse to it. The preferential loss of Si interstitials keeps electrically active dopant fixed in the lattice by inhibiting the "kick out" reaction that makes such dopant atoms mobile and inactive. The interstitial loss rate is controlled by the introduction of an additional step in the annealing process. The surface chemistry also changes the interaction of electrically charged defects with charges at the surface by greatly reducing the charge buildup at the surface and therefore reducing the surface repulsion effect, which increases the activated dopant concentration.

Applications

This technology can be applied to almost any product that uses higher end (< 90 nm) integrated circuits. Not relevant to technologies that use lower resolution since current pn junction technology is acceptable.

Examples of such applications include:

• Computers
• Communications
• Electronics

Benefits

• Pn junction with reduced depth and increased dopant activation: Leads to transistor devices with higher performance
• Compatible with current manufacturing technologies: Avoids the large costs associated with paradigm-changing technologies
• Adjusted loss rate of interstitials to the surface: Offers highly controllable mechanism for defect engineering.

Dr. Hubler has developed a novel design of nano-capacitors that employs Coulomb Blockade to suppress self-discharge and increases dielectric strength. Based on Dr. Hubler's research, nano-capacitors could have several orders of magnitude higher energy density than chemical batteries, but they suffer from short self-discharge time. Derived from quantum physics, this technology shows great potential to make nano-capacitors closer to real application.

This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device.

The invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.